Arithmetic Logic Unit

Project Details

Project name:Arithmetic Logic Unit

Name: Jiabin Lin

Partner: Rongdi Zhu

Class: ECEN 2350 digit logic

Language: Verilog

Software: Quartus Prime

Hardware: Det10-Lite

Introduction

This project contained three small parts of the code, arithmetic, logic, and comparison. We connected these parts of code together with a multiplexer. The overall idea is to connect the outputs of the three parts with a multiplexer, then we take the output of the multiplexer and input to the seven-segment display. We use the Key0 and Key1 as the switch of the 'Top multiplexer' to select the input of each block.

Figure 1: Block Diagram of the top level design

Logical block diagram:

We take the input from the switch [7:0] and assign them to X[3:0] and Y[3:0]. Also, switch 8 and 9 are used to control the multiplexer to display the each block.

Comparison block diagram:

we connect the four block diagrams: Equal, Greater, Lesser and Max with a multiplexer and use the switch 8 and 9 to control the output of the multiplexer.

Arithmetic block diagram:

we connect Adder, Subtracter, Divider, and multiplier together with a multiplexer and use switch 8 and 9 to control the switch of the multiplexer.

Top level block diagram:

we connect Logical, Arithmetic, and Comparison together and use key0 and key1 as the switch to control the output of the multiplexer, and then we take the output of the multiplexer to the input of seven-segments, allowing us to test the code on Det10-lite.

Seven-segment decoder:

Figure 2: Seven-segment display test

Figure 3: Truth table for seven-segment decoder

This is a seven segment decoder. We inputted four bits binary number and outputted seven different results(Columns). The truth table above is how we initially designed, however, due to the special design of the det10-lite, we had to reverse the code order and invert the bit number so it would display correctly.

The picture shows how this works when I turn on X[3:0] and Y[1] and Y[2]. This would be the case of 6F. When Y equals 0110 and X equals 1111, the truth table will output 6F.

Arithmetic:

In Arithmetic, we have four small diagrams. They are Add, Subtract, Multiply by 2 and Divide by 2.

-Add:

We design the code with one input and two outputs. First, we input an eight-bit number by using the switches 0-7 in the det10-lite, then we assign them to two new four-bit variables and we get X[3:0] and Y[3:0]. Then we add X[3:0] and Y[3:0] together. Since the pattern of the result of add acts like an XOR gate, we can use these patterns to create a for loop. The for loop runs bit by bit and gives us the result f = X & Y & C. Then we check if the result has carry out by checking x&y, x&c and y&c. If either one has the output 1, then we have carry out, therefore, we assign it to the next position of the carryout. If we have 5 carry out, we assign them to the overflow and use the multiplexer to light the LED 9.

-Subtract:

The idea of subtracting is similar to Adding. Subtracting a number is like adding a negative number. So we invert the four-bit input Y.

-Multiply by 2:

If we multiply the binary by two, the result will be shifted left by one bit. Therefore, we shifted the eight bit input to the left by one.

-Divide by 2:

If we divide the binary by two, the result will be shifted right by one bit. Therefore, we shifted the eight bit input to the right by one.

Logical:

In logical, we have four blocks of code. And gate, nor gate, xor gate, and inverter.

-And gate:

We take eight inputs from the switch and divide them into four bits X and four bits Y. The truth table for And gate is shown below. We compare each input X and Y bit by bit, and output the answer.

Figure 4: The truth table for And gate

-Or gate:

Similarly, we input eight bits of input and divide into X and Y. Then use the truth table of or gate to compare bit by bit and get the result.

Figure 5: The truth table for or gate

-Xor gate:

We compare bit by bit of the two four bits input by using the truth table of xor gate to get the result.

Figure 6: The truth table for xor gate

-Nor gate:

We take the entire input and invert the input completely.

Figure 7: The truth table for nor gate

Comparison:

In this block, we have four blocks of code as well. They are equal, greater, less and max.

-Equal:

We check if the code is equal by comparing the bit of the input. If true, we set the first 4 bits equal to 0001, and last four bits equal to 0000, otherwise, set X = 0000 and Y = 0000; this means return 1 if true, otherwise, return 0.

-Greater:

We check if the input of X is greater than the input of Y. If true, we set the first 4 bits equal to 0001, and last four bits equal to 0000, otherwise, set X = 0000 and Y = 0000. This means return 1 if true, otherwise, return 0.

-Less:

Similar to Greater and Equal, we check if X is less than Y. If true, we set the first 4 bits equal to 0001, and last four bits equal to 0000. Otherwise, set X = 0000 and Y = 0000. This means return 1 if true, otherwise, return 0.

-Max:

Like the greater function, we compare the inputs and find the bigger values. Then we assign the bigger value to the output and display its value on the seven-segment.

Block Diagram from the RTL:

Figure 8: Block diagram from the RTL view

This is the screenshot from the RTL viewer from our code. This diagram completely matches what we wanted to design. There are 10 switches, the first seven control the input of X and Y. Switches 9 and 10 become the switch of the comparison, logical, and Arithmetic's multiplexer. Key0 and key1 are switches of the top multiplexer. Assign the output of the top multiplexer to seven-segments' input, then to the seven-segment. Display them into the seven segments encoder. In Arithmetic, in case we have overflow, we assign the overflow output from each session to the multiplexer and assign the output to the LED 9. So the LED9 will be on if there is an overflow. For the purpose of better reading, we assign SW[9:8] and KEY[1:0] to HEX4 and HEX5, so we could read the working block from the HEX4 and 5. We also assign the output to both seven-segment and LEDR[7:0] so that we could read in both binary and Hexadecimal.

Figure 9: Table for the multiplexers switch and their corresponding blocks

Result:

Figure 10: Logical And gate, input X=4'b1011 and Y=4'b1101 output 4'b1001 Figure 11:Logical OR gate, input X=4'b1011 and Y=4'b1101 output 4'b1111

Figure 12: Logical Xor gate, input X=4'b1011 and Y=4'b1101 output 4'b0110 Figure 13: Logical Inverter, inputX=8'b11011011 output8'b00100100

Figure 14: Comparison equal block, input X=4'b1011 and Y=4'b1101 output 0 Figure 15: Comparison greater block, input X=4'b1011 Y=4'b1101 and meaning they are not equal output 0 meaning X is not greater than Y.

Figure 16: Comparison less block, input X=4'b1011 and Y=4'b1101 output Figure 17: Comparison Maximum block, input X=4'b1011 and Y=4'b1101 output 1 meaning X is less than Y. output 0 and d in hexadecimal meaning the greatest input is 4'b1101.

Figure 18: Arithmetic addition block, input X=4'b1011 and Y=4'b1101 output Figure 19: Arithmetic subtraction block, input X=4'b1011 and Y=4'b1101 0 meaning X plus Y equal 4'b11000, in Hexidecimal is 1 and 8 output 6'b111110 in 2's complement. LED9 is on indicate that there is overflow

Figure 20: Arithmetic multiplyby2 block, input X=8'b11011011 which is 219 in decimal, Figure 21: Arithmetic divideby2 block, input X=8'b11011011 which is 219 in

output b and 6 in hexadecimal, which is 8'b10110110 in binary; the overflow indicator decimal, output 6 and d in Hexidecimal. In binary is 8'b01101101. LED9 on

is on meaning the result should be 9'b110110110, which is 438 in decimal. indicate that there is remainder. 219 divide by 2 equal 109 remainder of 1.

Conclusion:

This is our first time coding in Verilog, We have some hard time figuring out some problems. For example, no print function in this case makes it harder to debug. Not setting up top level function leads the entire function not responding on any inputs. I believe the most important part of coding in Verilog is to design the entire code first, this is also the hardest part. However, once we have the all the design be readied, everything would be very clear. This is overall a very fun project, we spent several days doing this, trying to figure out the course concepts and learning to code in Verilog together, we have met so many problems, but we solved most of them eventually. This is a very fun project and we learnt a lot from it.