Reaction Timer

Reaction timer

Project Details

Title: Reaction timer

Class: Digital Logic

Semester: Spring 2018

Software: Quartus Prime Lite Edition

Hardware requirements: DE10-Lite

Programming language: Verilog

Introduction:

The main purpose of this project is to create a reaction timer in DE10-Lite. I used Verilog as the programming language to execute this program. The design of the reaction timer in DE10-Lite will have the start button. The user can press the start button KEY[0], then the system will generate some random time before it displays the counting timer. The user can press KEY[0] in the DE10-Lite board to stop the timer as soon as the user sees the counter has started counting or LEDR7,LEDR8,LEDR9 are flashing. Then the timer will stop counting and automatically save the best time to the system. The user can display the highest score by turnning on SW[2]. If there is a better score, the system will update it.

Figure 1: Reaction timer block diagram

Above is the reaction timer block diagram, I took the 50M Hz clock from the system. Then I wrote the clock divider to slow the clock down, the clock divider is basically counting 25000 positive edges to generate an alternate output, the 50M clock will slow down 25000 times. The clock divider connected to downcounter function and BCD_counter function. The countdown function takes the random number of LFSR, and then counts the number one by one until it hits zero, then it triggers the BCD_counter. The BCD counter takes the slow clock. When every slow positive clock occurs, the counter will start counting until the right-most seven-segment hits 9, then we start the next seven-segment counting. When the user presses the stop button KEY[0], the BCD_counter will stop running and will go to the highest score function to compare and check if the highest score is updated. The user can choose to go to the counter or the highest score by turning on or of SW[2].

State Machine Diagram

Figure 2: State machine Diagram

Above is the design of the state machine. If the user presses the KEY[0] in De10-Lite, it will activate the LFSR and the countdown function will start to count down. When the countdown is completed, the state machine will active BCD counter. When key[0] is pressed. The BCD counter will stop working and display the reaction time. If the user presses SW[2], it could switch to the highest score. SW[2] clears every data and bring the state to idle.

Result

This reaction timer functions quiet well. The only problem is the highest score displayment. When SW[2] is on, it will display some random time that we did not input. My initial design was to use the 2 to 1 multiplexer. Using SW[2] to control the displayment, BCD counter and Highest score as the inputs. I still have problem of finding the issues so far.

Video

Conclusion

With this project, I have gained more experience in Verilog coding, and it has helped me understand class concepts such as finite state machine, latch, and flip-flop. This project was pretty hard in general, the hardest thing in this project was to design a clear state machine and its code. I believe that a clear design before coding is critical. This project also makes me realize that I should test every part of coding before connecting every code together, otherwise, it will be very hard to debug. especially in verilog. Overall, this is a very interesting and cool project that applies the classroom concept to something real.